The IEEE 1149.1 Joint Test Action Group (JTAG) standard sets forth a protocol for using a test-access port (TAP) controller to perform various tests, such as boundary scan tests, and to interface with circuits that perform built-in self-tests. JTAG has been widely used to test printed circuit boards, integrated circuits and other circuits that include circuit modules often referred to as embedded “instruments”. JTAG tests are typically created in-house by instrument manufacturers or designers.
Modern integrated circuits tend to combine instruments from many different sources onto the same die for packaging as a chip. A chip designer must be familiar with the operation of the individual instruments in order to connect them together properly. Further, the chip designer should be able to test the individual instruments, which are not normally accessible at the top (e.g., chip) level of the completed design. The IJTAG standard addresses this concern by providing a standard protocol in which the JTAG TAP controller is used to interface with instruments. IJTAG provides an Instrument Connectivity Language (ICL) by which a designer can specify how circuit blocks are interconnected, including the interconnections between instruments in a chip. In contrast to hardware description language (HDL) definitions, ICL definitions are not detailed descriptions of the instrument's structure and behavior, but are instead abstract, hierarchical definitions of signals, registers, and input or output (I/O) ports needed to operate the instrument. ICL definitions include information necessary for performing read, write or scan operations on the instrument.
IJTAG also provides a Procedural Description Language (PDL) by which a designer defines the syntax and semantics of read, write or scan operations with respect to a circuit device's I/O ports. ICL and PDL definitions may be specified at the instrument level. PDL definitions may include test commands that apply test patterns to the instruments. Integrating the instrument level PDL definitions into a chip design generally requires using a software based, electronic design automation (EDA) tool to “retarget” the instrument level PDL definitions by translating operations specified in PDL to the top level, using hierarchical descriptions defined in ICL as a reference. This retargeting process is sometimes referred to as migration and is not limited to PDL definitions; migration can also refer to the overall process of translating instrument level data to top level data, to produce data that can be input to a simulator for simulating the chip. Thus, the migration of test patterns may include, in addition to PDL operations, the translation of boundary scan instructions or other instrument-specific test data not specified in ICL or PDL.
FIG. 1 is a block diagram of a chip model 100 that illustrates the relationships between the ICL and PDL definitions throughout the chip hierarchy. The model 100 includes instruments 120A to 120N, which collectively form a module 110 within the chip. For simplicity, only one module is shown. Additionally, instruments need not be grouped together, but instead may be stand-alone within the chip. The instruments include respective ICL definitions 122A to 122N and respective PDL definitions 124A to 124N. These instrument level definitions are generally supplied by an instrument manufacturer for use by the chip designer. A chip designer or other entity that integrates these instruments into the module 110 can also specify ICL definitions 112 and PDL definitions 114 for the module. A migration tool would need to translate the instrument level PDL definitions 124 to the module level PDL definitions 114 and, ultimately, to a chip level PDL definition 104. The translation process will reference the ICL definitions 102, 112 and 122 so that instrument operations, including test commands, can be converted to corresponding operations whose input parameters include I/O ports or registers at the chip level.
Errors in the ICL or PDL definitions can affect the validity of test pattern migration. These errors manifest themselves during simulation of the chip, when the application of migrated test patterns (such as retargeted PDL commands) produces discrepancies in the outputs of the chip. Mismatches between actual output values and expected output values can be due to several reasons including errors in test patterns and structural errors (for example, an error in an ICL definition that results in an attempt to access an instrument via a pin that does not, in fact, control the instrument). The chip designer then has the burden of debugging the errors, which can be difficult and time consuming. Accordingly, there is a need for ways to check the correctness of data relied upon for test pattern migration. Such a check should be performed as early as possible, preferably before simulation so that the designer can take appropriate corrective action. In this way, the designer can be confident that the migrated test patterns are being correctly applied to the instruments, in manners intended by the instrument manufacturers, to produce test results that correctly reflect the designed behaviors of the instruments.